According to high-integration techniques used in the fabrication of semiconductor devices, a metal interconnect line for transmitting an electrical signal to each device is so miniaturized that it causes problems such as increased resistance of the metal interconnect line, which is due to the decreased cross-sectional area and growing of parasitic capacitance owing to the reduction in gaps between adjacent interconnect lines. The increased resistance and the capacitance create a resistor-capacitor (RC) delay time. These effects will be a barrier factor in fabricating high-speed semiconductor devices. The parasitic capacitance in the gaps between the adjacent metal interconnect lines has to be reduced in order to fabricate the high-speed semiconductor device. To reduce this capacitance, application of a low dielectric layer or a metal interconnect line with low resistance is necessary. Particularly, technology for fabricating a metal interconnect line with low resistance may be further improved in process and equipment. Many studies and important projects for establishing the fabrication technology of the high-speed semiconductor device are therefore in progress.
Typically, an aluminum layer deposited by Physical Vapor Deposition (PVD) method was used as a metal layer for a metal interconnect line. However, the aluminum layer deposited using PVD does not solve the step coverage problem in a contact or via hole with a high aspect ratio. To solve this problem, fabrication processes of aluminum reflow and/or aluminum Chemical Vapor Deposition (CVD) have been developed. Using the aluminum reflow process, it is rather difficult to fill a contact hole with an aspect ratio equal to or greater than 3.0. Therefore, the aluminum CVD process is expected to be the prospective alternative for the step coverage problem.
Meanwhile, as the gaps between adjacent interconnect lines are narrowed, the intrinsic resistance of aluminum makes it difficult to improve the RC delay time. Thus a copper CVD process has been recently studied because the intrinsic resistance of copper is just about two-thirds of the intrinsic resistance of aluminum. However, deposition by the aluminum or copper CVD process is highly dependent on the lower layer of the substrate and, in spite of low occurrence of nucleation, after being formed nucleus grows rapidly. Thus, overhang problems such as void formation in a narrow via or contact hole occur. Additionally, the entire area of deposition is so rough that shortcomings such as a poor degree of reflection and low-step coverage take place. That is, defective alignment and overlay in an exposing process occur because of the increase in surface roughness of aluminum or copper and the decrease in a degree of reflection of aluminum or copper. Also, a void formation problem arises from the blockage of a contact hole by the bridge of aluminum crystals protruding from the contact hole. Owing to increase in surface roughness of aluminum deposited by the CVD and void formation from bridge on the side walls of a contact hole, aluminum or copper cannot be used as a filling metal in the conventional CVD process. Instead, after aluminum or copper as a metal for a seed layer is deposited, a via or contact hole is filled by a sputtering method of a PVD or CVD-PVD process.
Because apparatuses for the CVD-PVD process differ in process and control from apparatuses for each of the CVD and PVD processes, such apparatuses have to be built and controlled by an isolation device to avoid contamination. Although the research has been developing various surface processing methods prior to deposition and precursors, there is still much to improve in poor surface roughness and the low speed of deposition.
For a fabrication process of an interconnect line using only CVD in accordance with a prior art, after completion of an appropriate lithography process, de-gassing, etching, and barrier layer forming processes subsequently follow performed, and then a desired interconnect line is deposited by a CVD process.
FIG. 1a through FIG. 1d schematically illustrate, in cross-sectional views, the method of fabricating an interconnect line according to a prior art. Referring first to FIG. 1a, an inter-metal dielectric (IMD)/ pre-metal dielectric (PMD) layer 2 is deposited over a silicon substrate 1 with predetermined lower layer(s) (not shown) in order to thoroughly cover the lower layer(s) with a sufficient thickness. The IMD/PMD layer 2 is etched by a common photo lithography process and then a contact or via disclosing a predetermined hole over the silicon substrate 1 is formed.
Referring to FIG. 1b, a metal layer such as a Ti/TiN layer on inside of a contact hole 3 and over the insulating layer 2 is deposited with a uniform thickness and then the contact hole 3 is completely filled with a tungsten layer 5.
Referring to FIG. 1c, until a barrier metal layer 4 is exposed, a contact plug 5a is formed by etch back or polish of the tungsten layer 5 and then an aluminum layer 6 and an antireflection layer 7 such as a Ti/TiN layer are sequentially deposited on the contact plug 5a and the barrier metal layer 4 by a sputtering process.
As shown in FIG. 1d, an aluminum interconnect line 10 with a contact plug 5a is completed by removing some portion of an antireflection layer 7, an aluminum layer 6 and a barrier metal layer 4 using a common photo lithography process.
However, the above-mentioned process results in a number of problems.
Referring to FIG. 2, a sputter etch process is performed for the purpose of obtaining a stable via resistance by removing a native aluminum oxide layer “(22,23) of a substrate (20)” exposed under a via hole “in an IMD/PMD layer (21) before depositing a barrier metal layer (24)”. The sputter etch process enables a barrier metal layer and a tungsten layer to be completely filled without shadow effect of an overhang by slightly widening the mouth of a via hole.
Most of sputter etched particles are exhausted by a vacuum pump, but residual particles (32) are stuck in the inside wall of a sputter etch chamber (30). The particles (32) trapped in the inside wall of the chamber (30) grow larger until the particles fall (33) when the stress of the trapped particles become greater than the adhesion force between them. When they fall, if a sputter etch process is proceeding on a substrate (31), the fallen particles are deposited as impurities on the substrate. If the fallen impurities deposited on the substrate block a hole, it is impossible to deposit a barrier metal layer and a tungsten layer. It thus leads to short circuits between an upper metal layer and a lower metal layer and the semiconductor device malfunctions (FIG. 3).
The inside wall of a sputter etch chamber is made of quartz for electric insulation, so that the sputter etched particles have weak adhesion force. Impurity problem is therefore a grave concern in the sputter etch process.
U.S. Pat. No. 5,707,498, to Kenny King-Tai Ngan, discloses a method of depositing a film on a semiconductor workpiece in an inductively-coupled plasma sputtering chamber so as to avoid contamination of the film by material sputtered off the induction coil.
U.S. Pat. No. 6,306,247, to Cheng Chih Lin, discloses an apparatus and a method for preventing particle contamination in a plasma etch chamber equipped with a middle chamber by residual etchant gas.